1. Field of the Invention
The present invention relates to a semiconductor device having, particularly, an improved arrangement of a filed plate electrode (Fet), and a manufacturing method thereof.
2. Related Art
It has been well known that when a field plate electrode is provided for a semiconductor device, such as a field effect transistor, and is connected to the gate electrode thereof, the breakdown voltage of the semiconductor device can be improved.
FIG. 7 is a schematic perspective view showing one example of a conventional semiconductor device having a field plate electrode, and a semiconductor device 50 shown in FIG. 7 is, for example, a GaAs field effect transistor. A channel layer 52 is formed in the vicinity of a surface of a semiconductor substrate 51, and on this channel layer 52, a drain electrode 53 and a source electrode 54, each having an ohmic contact, and a gate electrode 55 having a Schottky contact are formed.
In addition, on the surface of the channel layer 52 between the drain electrode 53 and the source electrode 54, a surface passivation film (surface protective film) 56 composed, for example, of silicon nitride (SiN) is formed so as to cover the gate electrode 55, and furthermore, on the surface passivation film 56 between the drain electrode 53 and the gate electrode 55, a field plate electrode 57 is formed at a predetermined distance Lgf from the gate electrode 55.
Next, one example of a manufacturing method of the above semiconductor device 50 will be described. First, the drain electrode 53 and the source electrode 54, each having an ohmic contact, are formed on the channel layer 52 formed on the surface of the semiconductor substrate 51. Subsequently, a resist pattern having an opening for forming the gate electrode is formed on the surface of the channel layer 52 using a photolithographic technique or the like, and a metal film is formed over the entire surface thereof. The metal film other than that for forming the gate electrode 55 is thereafter removed by a lift-off method together with the resist film, thus the gate electrode 55 being formed.
Then, an SiN film used as the surface passivation film 56 is formed by, for example, a plasma CVD method over the entire surface of the channel layer 52 between the drain electrode 53 and the source electrode 54. Subsequently, after a resist pattern having an opening for forming the field plate electrode 57 has been formed on the surface passivation film 56, and a metal film has been then formed, the metal film other than that in the opening is removed by a lift-off method together with the resist film, thus the field plate electrode 57 being formed.
As a method for connecting the gate electrode 55 to the field plate electrode 57, the following example may be mentioned.
For example, there may be provided a method in which a connection pattern used for connection is formed on the surface passivation film 56. In this method, after a predetermined portion of the surface passivation film 56 covering the gate electrode 55 is removed by chemical dry etching or the like, the field plate electrode 57 and the above predetermined portion of the exposed gate electrode 55 are connected to each other by the connection pattern (not shown in FIG. 7) formed on the surface passivation film 56.
In addition, there is also provided an example, in which the connection is performed outside of the semiconductor device 50, as disclosed, for example, in Japanese Patent Laid-open Publication No. 2000-315804. In this example, unit filed effect transistors are disposed in series, in each of which a gate electrode and a field plate electrode are formed with a predetermined distance therebetween, so that a high output device is formed, and the gate electrode and the field plate electrode of each field effect transistor (FET) are connected to each other by way of a connection portion provided outside.
Furthermore, unlike the above structure in which the gate electrode and the field plate electrode are disposed separately, there may be further provided an example in which the gate electrode and the field plate electrode are integrated, for example, as disclosed in Japanese Patent Laid-open Publication No. 2001-230263. In this example, a field plate section having a portion protruding from the gate electrode toward the drain electrode side is formed, and a high dielectric material is disposed between the field plate section and the channel layer.
When the field plate electrode 57 connected to the gate electrode 55 is disposed, the breakdown voltage of the semiconductor device 50 such as a field effect transistor is improved. In the structure in which the gate electrode 55 and the field plate electrode 57 are formed with a predetermined distance Lgf provided therebetween as shown in FIG. 5, the breakdown voltage characteristic varies depending on the distance Lgf. Hence, in order to obtain desired breakdown voltage characteristic, it is necessary to reduce an error of the distance Lgf and to form the gate electrode 55 and the field plate electrode 57 with high precision at predetermined positions.
However, in the above conventional manufacturing method, since the gate electrode 55 and the field plate electrode 57 are formed in different steps, it has been difficult to highly precisely maintain the distance Lgf between the gate electrode 55 and the field plate electrode 57. As a result, the breakdown voltage characteristic varies, and hence, the manufacturing yield of the semiconductor device 50 is decreased.
In addition, when the field plate electrode 57 is provided, a parasitic capacitance is generated between the field plate electrode 57 and the channel layer 52. In particular, as is the method disclosed in the Japanese Patent Laid-open Publication No. 2001-230263, when the gate electrode and the field plate electrode are integrated, the parasitic capacitance is increased. This parasitic capacitance acts as a feedback capacitance to the gate electrode 55 used as a signal input side, and hence, high frequency characteristic of the semiconductor device is adversely influenced such that input/output characteristic of the semiconductor device in a high frequency region are degraded.